In one aspect, the inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell and device; and more particularly, in one aspect, to a semiconductor dynamic random access memory (“DRAM”) cell, array, architecture and/or device wherein the memory cell includes an electrically floating body in which an electrical charge is stored.
Briefly, by way of background, there is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Silicon-on-Insulator (SOI) is a material in which such devices may be fabricated on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET. SOI devices have demonstrated improved performance (for example, speed), reduced leakage current characteristics and considerable enhancement in scaling.
One type of dynamic random access memory cell is based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12 each consisting of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material/substrate). The insulation or non-conductive region may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge is accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of charge or carriers (for example, majority carriers) within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
As mentioned above, memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, an N-channel transistor. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, provides or results in a carrier concentration which is representative of a logic high or “1” data state. (See, FIG. 2A). Emitting or ejecting majority carriers 30 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, provides or results in a carrier concentration which is representative of a logic low or “0” data state. (See, FIG. 2B).
Notably, for at least the purposes of this discussion, logic high or State “1” corresponds to an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic low or State “0”. In contrast, logic low or State “0” corresponds to a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with a logic high or State “1”.
As mentioned above, conventional techniques write or program a logic low (State “0”) by removing majority carriers from body region 18 through either source region 20 or drain region 22 of electrically floating body transistor 14 of memory cell 12. In this regard, in one embodiment, majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 are removed from memory cell 12 through drain region 22. (See, FIG. 3A). A current 36 (electrons) flows from drain region 22 to source region 20 due to a channel forming in a portion of body region 18 immediately beneath the gate oxide when writing or programming a logic low (State “0”). Where the majority carriers (in this example, “holes”) 34 are removed from memory cell 12 through source region 20, current 36 (electrons) flows from source region 20 to drain region 22 as a result of channel formation when writing or programming a logic low (State “0”). (See, FIG. 3B).
Aside from the consumption of power, writing or programming data into memory cells of an array may also “disturb” adjacent cell memory cells in memory device 10. One technique to address the disturbance issue is to employ a two-cycle write or program technique. In this regard, in one embodiment, in the first cycle a logic low (State “0”) is written into all memory cells 12 connected to a word line 28; in the second cycle, a logic high (State “1”) is selectively written into memory cells 12 while an inhibit signal or voltage is applied to those memory cells 12 that are to remain at or maintain a logic low or State “0”. In this way, certain memory cells 12 connected to a given word line may be written or programmed to a logic low (State “0”) using a first word line voltage; and certain other memory cells 12, also connected to the given word line, may be written or programmed to a logic high (State “1”) using a second word line voltage. (See, for example, application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004, and entitled “Semiconductor Memory Device and Method of Operating Same”).
While electrically floating body transistors of memory cells (for example, SOI transistors) of the type described above exhibit low leakage current characteristics, such memory cells often consume a considerable amount of power when programming a logic low (i.e., removing charge carriers from the body of the SOI device). Moreover, many architectures and programming techniques tend to provide a two-cycle writing or programming techniques. This may reduce the speed or access time of the memory device, memory array, and/or memory cells. As such, there is a need for high performance floating body memory cells, devices and arrays having improved performance characteristics (for example, speed and/or programming window, programming current consumption), reduced leakage current characteristics and/or considerably enhanced scaling and density capabilities.